The ISA went through multiple incompatible versions as ideas evolved, both at the assembly language level and in the binary encoding.

The first RISC-V chip you could buy, SiFive’s FE310, came out in December 2016 on the HiFive1 Arduino-clone board. It’s just a microcontroller, with only the User mode instructions. Machine mode and Supervisor mode instructions and CSRs were under active development and incompatible changes until not long before the base ISA was ratified (frozen, published) in July 2019. SiFive put out a Linux SBC, HiFive Unleashed (with the FU540 SoC) in early 2018, with about 500 made, but that was experimental and they were prepared for it to be orphaned if incompatible changes were made to the ISA before ratification.

I think the fair “RISC-V origin” date is somewhere between the publication of Privileged Architecture 1.10 in May 2017 and ratification in July 2019. For sure not 2010.

On another topic, I note that 8086 was by far the least CISCy of the CISC chips and this is a big reason it was able to survive into the RISC era (the billions from the IBM PC and clones helped a lot too!). VAX, M68000, Z8000, NS 16032/32032 were just too complex to make fast.

“since the 90s, x86 processors also include SIMD (Single Instruction, Multiple Data) instructions for parallel processing tasks. This allows multicore processors to run quickly as well.” Those are absolutely unrelated.

“RISC-V architecture is open-source and royalty-free, allowing anyone to design and manufacture RISC-V processors without paying licensing fees. It’s really like the Linux of ISAs.” True, but designing your own costs far more than licensing a design from one of the dozen or so commercial RISC-V core providers (with very similar business models to Arm)

Quite right – thanks, tozo!