{"id":5730,"date":"2023-10-24T15:17:33","date_gmt":"2023-10-24T15:17:33","guid":{"rendered":"https:\/\/picockpit.com\/raspberry-pi\/?p=5730"},"modified":"2023-11-08T16:32:14","modified_gmt":"2023-11-08T16:32:14","slug":"arm-vs-risc-v-vs-x86","status":"publish","type":"post","link":"https:\/\/picockpit.com\/raspberry-pi\/zh\/arm-vs-risc-v-vs-x86\/","title":{"rendered":"ARM vs. RISC-V vs. x86 \u7b80\u5355\u6307\u5357"},"content":{"rendered":"\n
\"RISC-V<\/figure>\n\n\n\n

Introduction<\/strong><\/h2>\n\n\n\n

We’ve been talking a lot about Raspberry Pi 5<\/a> here at PiCockpit, of course. The other day, I found a discussion about Raspberry Pi 5 that centered on the Pi’s ARM architecture and how that stacks up with RISC-V architecture. For years, people have talked about Raspberry Pi’s compatibility with x86. But what about a RISC-V Pi?<\/p>\n\n\n\n

This is especially interesting, because Raspberry Pi is a member of RISC-V International<\/a>.<\/p>\n\n\n\n

As is Arduino, actually.<\/p>\n\n\n\n

So there’s potentially a future for RISC-V architecture chips on Raspberry Pis<\/a>. However, I wouldn’t hold my breath hoping for a x86 Raspberry Pi.<\/p>\n\n\n\n

After all, in a recent discussion posted by Raspberry Pi<\/a>, Gordon Hollingworth said, “People are like, ‘Well, could you do that? Can you make up an x86 Raspberry Pi?<\/a>‘ It\u2019s like, ‘Oh, God, it\u2019d be a lot of work.’ You could, but…”<\/p>\n\n\n\n

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\"An<\/figure>\n<\/div>\n\n\n

<\/p>\n\n\n\n

So I thought it was time to go over some of the key differences and similarities between RISC-V, ARM, and x86 architectures. I’ll go over their history, their benefits and drawbacks, and what distinguishes them from one another.<\/p>\n\n\n\n

At the end, you’ll get a sense of why that would be so much work to make an x86 Raspberry Pi, but why a RISC-V Raspberry Pi isn’t out of the question.<\/p>\n\n\n\n

Overview<\/strong><\/h2>\n\n\n\n
<\/th>RISC-V<\/strong><\/th>ARM<\/strong><\/th>x86<\/strong><\/th><\/tr><\/thead>
Origin<\/strong><\/td>RISC-V International<\/td>Arm Ltd.<\/td>Intel and AMD<\/td><\/tr>
Instruction Set<\/strong><\/td>RISC (Reduced Instruction Set Computing)<\/td>RISC (Reduced Instruction Set Computing)<\/td>CISC (Complex Instruction Set Computing)<\/td><\/tr>
Byte Order<\/strong><\/td>Typically little-endian (user-configurable)<\/td>Typically bi-endian (user-configurable)<\/td>Little-endian<\/td><\/tr>
Applications<\/strong><\/td>Embedded systems, IoT devices, custom solutions<\/td>Mobile devices, embedded systems, servers<\/td>Desktops, laptops, servers, workstations<\/td><\/tr>
Licensing Model<\/strong><\/td>Open-source, royalty-free licensing<\/td>ARM licenses its designs to manufacturers<\/td>Intel and AMD produce their own chips<\/td><\/tr>
Ecosystem<\/strong><\/td>Developing ecosystem, open-source initiatives<\/td>Large ecosystem, extensive third-party support<\/td>Large software and hardware ecosystem<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

<\/p>\n\n\n\n

So now let’s go through each of these points.<\/p>\n\n\n\n

Origin<\/strong><\/h2>\n\n\n\n

And let me first begin here with x86, as it’s the oldest of the three. The x86 architecture goes back to 1978, when Intel launched the 8086 family. The x86 architecture was CISC, which was hot at the time. Today, x86 architecture continues to be under the control of Intel, along with AMD.<\/p>\n\n\n\n

The ARM architecture got its start 7 years later, when Acorn Computers Ltd. released the ARM1. Acorn Computers is no longer around today, but their ARM architecture lives on through Arm Ltd. Arm Ltd. now licenses out ARM architecture to other companies.<\/p>\n\n\n\n

In comparison, RISC-V is extremely new, beginning in just 2010 at the University of California, Berkeley. In 2015, a bunch of tech companies (everyone from IBM to Google to Nvidia) came together to found the RISC-V Foundation. In 2020, due to geopolitical issues, the RISC-V Foundation moved to Switzerland and became RISC-V International.<\/p>\n\n\n

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\"RISC-V<\/figure>\n<\/div>\n\n\n

Instruction Set<\/strong><\/h2>\n\n\n\n

First, let me clarify the difference between RISC and CISC.<\/p>\n\n\n\n

RISC processors use a small, optimized set of instructions, each taking a single clock cycle, enabling faster and more predictable execution.<\/p>\n\n\n\n

In contrast, CISC processors have a larger and more diverse instruction set, often including complex instructions that may require multiple clock cycles, leading to potentially slower but more versatile performance in handling various tasks.<\/p>\n\n\n\n

So, RISC-V is RISC-based, obviously. But what sets it apart is the fact that it’s open-source.<\/p>\n\n\n\n

In their 2014 paper, Instruction Sets Should Be Free: The Case For RISC-V<\/a><\/em>, Krste Asanovi\u0107 and David A. Patterson compare RISC-V to Linux. The idea is that there is a fully open-source Instruction Set Architecture. So people should be able to manipulate it, play with it, and share it.<\/p>\n\n\n\n

Asanovi\u0107 and Patterson argue that this could drive innovation, better transparency, and lower costs.<\/p>\n\n\n\n

Now I should mention, although RISC-V itself is open-source, specific implementations of RISC-V can be both open-source or proprietary.<\/p>\n\n\n\n

ARM instructions are also RISC-based. However, since Arm Ltd. license out the architecture, they’re anything but open-source. As Asanovi\u0107 and Patterson put it: “An ARM license doesn\u2019t even let you design an ARM core; you just get to use their designs.” Although it’s not quite that simple, that is generally the case.<\/p>\n\n\n\n

Above, I said that x86 architecture is CISC-based. That’s true, but I should mention that, since the 90s, x86 processors also include SIMD (Single Instruction, Multiple Data) instructions for parallel processing tasks. This allows multicore processors to run quickly as well.<\/p>\n\n\n\n

After all, the world’s fastest supercomputer – Frontier – is x86-based. <\/p>\n\n\n\n

But the world’s second-fastest supercomputer – Fugaku – is ARM-based.<\/p>\n\n\n\n

A lot of people argue that the distinction between RISC and CISC isn’t very important today. Because modern processors are so powerful, they say that the differences between these types of instruction sets have virtually disappeared. However, in their call for RISC-V, Asanovi\u0107 and Patterson argue that “[i]t\u2019s been decades since any new CISC ISA has been successful” and so it makes more sense to go with a RISC-based architecture.<\/p>\n\n\n\n

Byte Order<\/strong><\/h2>\n\n\n\n

Endianness refers to the byte order in which multibyte data types are stored in computer memory. <\/p>\n\n\n\n

In little-endian systems, the least significant byte is stored at the lowest memory address, while in big-endian systems, the most significant byte is stored at the lowest address.<\/p>\n\n\n\n

Endianness is super important when you want to exchange data between processors. If you send information from a big-endian system to a little-endian system, then your data could easily become corrupted if you don’t convert it properly.<\/p>\n\n\n\n

RISC-V is typically little-endian. That’s something you can configure however, if you want your RISC-V to have a big-endian byte order.<\/p>\n\n\n\n

ARM architecture can be either little-endian or big-endian, depending on the specific implementation. Like RISC-V, you can configure an ARM chip to be big-endian.<\/p>\n\n\n\n

Raspberry Pis are, by default, little-endian. You can check this out yourself by going to your Raspberry Pi, opening up the terminal, and running:<\/p>\n\n\n\n

<\/p>\n\n\n\n

<\/circle><\/circle><\/circle><\/g><\/svg><\/span><\/path><\/path><\/svg><\/span>
lscpu<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n
<\/p>\n\n\n\n
The x86 architecture is little-endian. But unlike RISC-V and ARM architecture, you can’t change this. Being little-endian is a feature of x86 architecutre.<\/p>\n\n\n\n
Applications<\/strong><\/h2>\n\n\n\n
I want to go back to the Asanovi\u0107 and Patterson article for a moment. Although the article is from 2014, it makes a very important point. They assert that “[w]hile the 80×86 won the PC wars, RISC dominates the tablets and smart phones of the PostPC Era; in 2013 more than 10 [billion] ARMs were shipped, as compared to 0.3 [billion] 80x86s.”<\/p>\n\n\n\n
That’s a huge discrepancy, but it also shows that the applications for an architecture help define its significance. That’s why it was such a big deal in 2020 when Apple unveiled the M1 chip for its new computers. If Apple was switching from x86 to ARM, then what does that mean for x86’s future?<\/p>\n\n\n\n
Nevertheless, x86 still dominates the computer market. Desktops, laptops, and servers all continue to primarily rely on x86 architecture.<\/p>\n\n\n\n
ARM, meanwhile, is typically in smartphones and tablets. And, of course, in your humble Raspberry Pi. However, it looks like ARM might start to take over the computer world as well<\/a>.<\/p>\n\n\n\n
<\/p>\n\n\n
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\"smartphone<\/figure>\n<\/div>\n\n\n
<\/p>\n\n\n\n
RISC-V is clearly hoping to eke out a share of the ARM architecture’s space, but it still remains open on what it could do in the future. Both universities and industry are investing in RISC-V and watching its development closely.<\/p>\n\n\n\n
If ARM has started chipping away at x86, will RISC-V start chipping away at ARM?<\/p>\n\n\n\n
Licensing Model<\/strong><\/h2>\n\n\n\n
The most restrictive of the three is the x86. As I mentioned above, really only two companies produce x86 architecture chips – Intel and AMD. The chips aren’t customizable and the architecture is wholly proprietary.<\/p>\n\n\n\n
The ARM architecture works differently, because of the licensing model. A typical ARM license doesn’t allow you to create an ARM architecture design. However, there are exceptions, because Apple’s M1 chip was predictably customized to their desires.<\/p>\n\n\n\n
RISC-V architecture is open-source and royalty-free, allowing anyone to design and manufacture RISC-V processors without paying licensing fees. It’s really like the Linux of ISAs.<\/p>\n\n\n\n
Interestingly, though, Intel and AMD are both members of RISC-V International. So clearly they also think that it’s valuable to contribute to RISC-V architecture.<\/p>\n\n\n\n
Ecosystem<\/strong><\/h2>\n\n\n\n
RISC-V’s ecosystem is growing rapidly, with many companies and researchers contributing to open-source projects and developing RISC-V-based products. <\/p>\n\n\n\n
Although the software ecosystem isn’t huge at the moment, it is growing. You can see its developments with the RISE project<\/a> (RISE stands for RISC-V Software Ecosystem).<\/p>\n\n\n\n
When it comes to ARM and x86, they both dominate in their respective markets. The ecosystems for both are well-established and vast. <\/p>\n\n\n\n
This is one of the clearest drawbacks with RISC-V. It simply doesn’t have the wide adoption of the other two and competition here is fierce.<\/p>\n\n\n\n
RISC and CISC in Action<\/strong><\/h2>\n\n\n\n
In this fantastic video from The [Fill in the Blank] Programmer<\/a>, you can see exactly how RISC and CISC works on the level of Assembly Code.<\/p>\n\n\n\n
Here you can see the difference between RISC and CISC in detail. <\/p>\n\n\n\n
On ARM and RISC-V, the Assembly Code has shorter lines, but more of them. On x86, the lines of Assembly are more complex, but there are fewer of them.<\/p>\n\n\n\n
The video goes through how the GCC compiler and the Clang compiler transforms C++ code into Assembly for each of the three ISAs – ARM vs. RISC-V vs. x86_64. Check it out:<\/p>\n\n\n\n
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